Instruction Encoding

This page shows binary code for each instruction. This instruction table is used by Toshi Disassembler. The table shows binary code (in hex) followed by the instruction it represents. First byte is the operation code. Depending on instruction the opcode is followed by zero, one, two or three arguments. In the table argument type and length is encoded. For example %16u represents a 16bit argument of type "u" (unsigned). Arguments that represent changes to the program counter(PC) are of type "a"(%7a), because the argument is added to the address of the next instruction, not current value of PC. For example "bra 0" is equivalent to "nop", not an infinite loop. Argument %1x is one bit and represents either x or y register when it's 0 or 1 respectively.

hex code	opcode	arguments
00	nop
01%16u	jsr	&0a
02	xch	a, b
03%16u	jmp	&0a
04	shr	d
05	di
06	shl	d
07	ei
08	add	a, b
09	sub	a, b
0A%8u	st	x, $&0a
0B	cmp	a, b
0C	add	x, a
0D	add	y, a
0E	add	x, b
0F	add	y, b
10	shr	a
11	shr	b
12	shl	a
13	shl	b
14	rorc	a
15	rorc	b
16	rolc	a
17	rolc	b
18	shra	a
19	shra	b
1A	ld	a, [y]
1B	ld	d, [y]
1C	inc	x
1D	inc	y
1E	dec	x
1F	dec	y
20	shr	x
21%1x%7u	jsr	&0a + &1a
22	shl	x
23%1x%7u	jmp	&0a + &1a
24%1x%7u	rorc	&0a + &1a
25	clrv
26%1x%7u	rolc	&0a + &1a
27	setv
28%1x%7u	shra	&0a + &1a
29%1x%7u	st	s, &0a + &1a
2A%1x%7u	st	x, &0a + &1a
2B%1x%7u	st	y, &0a + &1a
2C	mov	x, s
2D	inc	s
2E	mov	s, x
2F	dec	s
30%8u	shr	$&0a
31%8u	jsr	$&0a
32%8u	shl	$&0a
33%8u%8u	ld	#&0a, $&1a
34%8u	rorc	$&0a
35%3d%5u%8a	tbbs	b.&0a, $&1a, &2a
36%8u	rolc	$&0a
37%3d%5u%8a	tbbc	b.&0a, $&1a, &2a
38%8u	shra	$&0a
39%8u	st	s, $&0a
3A%8u	st	x, $&0a
3B%8u	st	y, $&0a
3C	mov	x, d
3D	mov	y, d
3E	mov	d, x
3F	mov	d, y
40%8a	bra	&0a
41%8a	brn	&0a  ; branch never; used similar to CMP Instructions
42%8a	bgt	&0a
43%8a	ble	&0a
44%8a	bcc	&0a
45%8a	bcs	&0a
46%8a	bne	&0a
47%8a	beq	&0a
48%8a	bvc	&0a
49%8a	bvs	&0a
4A%8a	bpz	&0a
4B%8a	bmi	&0a
4C%8a	bgea	&0a
4D%8a	blta	&0a
4E%8a	bgta	&0a
4F%8a	blea	&0a
50	dec	a
51	dec	b
52	clr	a
53	clr	b
54	neg	a
55	neg	b
56	inc	a
57	inc	b
58	cmpz	a
59	cmpz	b
5A	mov	b, a
5B	mov	a, b
5C	mov	ocr, a
5D	mov	a, ocr
5E	adj	a
5F	nmi
60%1x%7u	dec	&0a + &1a
61%8a	bsr	&0a
62%1x%7u	clr	&0a + &1a
63	ret
64%1x%7u	neg	&0a + &1a
65	clrc	c
66%1x%7u	inc	&0a + &1a
67	setc	c
68	push	d
69	xch	x, y
6A%1x%7u	xch	a, &0a + &1a
6B%1x%7u	xch	b, &0a + &1a
6C	push	a
6D	push	b
6E	push	x
6F	push	y
70%8u	dec	$&0a
71%3d%5u	tbs	bit&0a, $&1a
72%8u	clr	$&0a
73	reti
74%8u	neg	$&0a
75%3d%5u	clrb	bit&0a, $&1a
76%8u	inc	$&0a
77%3d%5u	setb	bit&0a, $&1a
78	pull	d
79%16u	cmp	#&0a, $&1a
7A%8u	xch	a, $&0a
7B%8u	xch	b, $&0a
7C	pull	a
7D	pull	b
7E	pull	x
7F	pull	y
80%8u	addc	a, #&0a
81%8u	mul	a, #&0a
82	st	a, [y]
83	wait
84%8u	subc	a, #&0a
85%8u	div	d, #&0a
86%16u	ld	d, #&0a
87%16u	add	d, #&0a
88%16u	sub	d, #&0a
89%16u	cmp	d, #&0a
8A	st	d, [y]
8B%16u	ld	s, #&0a
8C%16u	cmp	x, #&0a
8D%16u	cmp	y, #&0a
8E%16u	ld	x, #&0a
8F%16u	ld	y, #&0a
90%8u	addc	a, $&0a
91%8u	mul	a, $&0a
92%8u	st	a, $&0a
93%8u	st	b, $&0a
94%8u	subc	a, $&0a
95%8u	div	d, $&0a
96%8u	ld	d, $&0a
97%8u	add	d, $&0a
98%8u	sub	d, $&0a
99%8u	cmp	d, $&0a
9A%8u	st	d, $&0a
9B%8u	ld	s, $&0a
9C%8u	cmp	x, $&0a
9D%8u	cmp	y, $&0a
9E%8u	ld	x, $&0a
9F%8u	ld	y, $&0a
A0%1x%7u	addc	a, &0a + &1a
A1%1x%7u	mul	a, &0a + &1a
A2%1x%7u	st	a, &0a + &1a
A3%1x%7u	st	b, &0a + &1a
A4%1x%7u	subc	a, &0a + &1a
A5%1x%7u	div	d, &0a + &1a
A6%1x%7u	ld	d, &0a + &1a
A7%1x%7u	add	d, &0a + &1a
A8%1x%7u	sub	d, &0a + &1a
A9%1x%7u	cmp	d, &0a + &1a
AA%1x%7u	st	d, &0a + &1a
AB%1x%7u	ld	s, &0a + &1a
AC%1x%7u	cmp	x, &0a + &1a
AD%1x%7u	cmp	y, &0a + &1a
AE%1x%7u	ld	x, &0a + &1a
AF%1x%7u	ld	y, &0a + &1a
B0%16u	addc	a, &0a
B1%16u	mul	a, &0a
B2%16u	st	a, &0a
B3%16u	st	b, &0a
B4%16u	subc	a, &0a
B5%16u	div	d, &0a
B6%16u	ld	d, &0a
B7%16u	add	d, &0a
B8%16u	sub	d, &0a
B9%16u	cmp	d, &0a
BA%16u	st	d, &0a
BB%16u	ld	s, &0a
BC%16u	cmp	x, &0a
BD%16u	cmp	y, &0a
BE%16u	ld	x, &0a
BF%16u	ld	y, &0a
C0%8u	add	a, #&0a
C1%8u	add	b, #&0a
C2%8u	and	a, #&0a
C3%8u	and	b, #&0a
C4%8u	sub	a, #&0a
C5%8u	sub	b, #&0a
C6%8u	or	a, #&0a
C7%8u	or	b, #&0a
C8%8u	xor	a, #&0a
C9%8u	xor	b, #&0a
CA%8u	ld	a, #&0a
CB%8u	ld	b, #&0a
CC%8u	cmp	a, #&0a
CD%8u	cmp	b, #&0a
CE%8u	cmpb	a, #&0a
CF%8u	cmpb	b, #&0a
D0%8u	add	a, $&0a
D1%8u	add	b, $&0a
D2%8u	and	a, $&0a
D3%8u	and	b, $&0a
D4%8u	sub	a, $&0a
D5%8u	sub	b, $&0a
D6%8u	or	a, $&0a
D7%8u	or	b, $&0a
D8%8u	xor	a, $&0a
D9%8u	xor	b, $&0a
DA%8u	ld	a, $&0a
DB%8u	ld	b, $&0a
DC%8u	cmp	a, $&0a
DD%8u	cmp	b, $&0a
DE%8u	cmpb	a, $&0a
DF%8u	cmpb	b, $&0a
E0%1x%7u	add	a, &0a + &1a
E1%1x%7u	add	b, &0a + &1a
E2%1x%7u	and	a, &0a + &1a
E3%1x%7u	and	b, &0a + &1a
E4%1x%7u	sub	a, &0a + &1a
E5%1x%7u	sub	b, &0a + &1a
E6%1x%7u	or	a, &0a + &1a
E7%1x%7u	or	b, &0a + &1a
E8%1x%7u	xor	a, &0a + &1a
E9%1x%7u	xor	b, &0a + &1a
EA%1x%7u	ld	a, &0a + &1a
EB%1x%7u	ld	b, &0a + &1a
EC%1x%7u	cmp	a, &0a + &1a
ED%1x%7u	cmp	b, &0a + &1a
EE%1x%7u	cmpb	a, &0a + &1a
EF%1x%7u	cmpb	b, &0a + &1a
F0%16u	add	a, &0a
F1%16u	add	b, &0a
F2%16u	and	a, &0a
F3%16u	and	b, &0a
F4%16u	sub	a, &0a
F5%16u	sub	b, &0a
F6%16u	or	a, &0a
F7%16u	or	b, &0a
F8%16u	xor	a, &0a
F9%16u	xor	b, &0a
FA%16u	ld	a, &0a
FB%16u	ld	b, &0a
FC%16u	cmp	a, &0a
FD%16u	cmp	b, &0a
FE%16u	cmpb	a, &0a
FF%16u	cmpb	b, &0a